1. Field of the Present Invention
The present invention relates to the field of Programmable Logic Devices. More particularly, the present invention relates to high speed and low noise circuits for macrocells of Programmable Logic Devices.
2. Description of the Prior Art
FIG. 1 depicts a typical circuit of a prior art Programmable Logic Device macrocell. As shown in FIG. 1, the typical macrocell circuit includes five logic stages comprised of a NOR logic 10, an Invertor logic 12, a MUX logic 14, a Latch 16, an Output Driver logic 18, and finally an output pad 20.
FIG. 2 shows a conventional implementation of the various logic stages of FIG. 1. As shown in FIG. 2, eight product terms P1 through P8 feed a conventional NOR gate 10A. Thereafter, the output of the NOR gate 10A is inverted and buffered by the two invertors of logic block 12A so as to provide a stronger drive for a conventional MUX 14A. Signal S1 of the MUX 14A selects between either the true or the inverse polarity of the output of the NOR gate 10A. Thereafter, a conventional latch 16A stores the data received from MUX 14A. Subsequently, the data stored in latch 16A is passed on by the output predriver 18A to the output driver 18B. Output driver 18B then charges or discharges output pad 20 and its parasitic capacitance represented by a single lumped capacitance 19. Thus, the conventional implementation of the macrocell circuit shown in FIGS. 1 and 2 requires five logic stages.
This typical implementation of NOR'ing of the product terms P1 through P8, and then inverting, MUX'ing, latching, and outputting the NOR'ed result is too slow and produces too much noise on the supply voltage and ground lines. To illustrate these problems, a typical implementation of the NOR gate 10A of FIG. 2 is shown in FIG. 3. As shown in FIG. 3, the charge path of the NOR gate 10A consists of eight P-channel transistors. Since the resistive path from the output of the NOR gate 10A to the supply voltage is equivalent to the series resistance of the eight P-channel transistors, the rise time of the output 10B of the NOR gate 10A is very long. This long rise time in turn necessitates the use of the double inversion circuit 12A of FIG. 2 in order to reduce switching times at the input of the MUX 14A.
Furthermore, the conventional output predriver 18A and output driver 18B of FIG. 2 result in "noisy" ground and supply voltage lines. This noise is generated by the sudden charging or discharging of the output capacitive load, represented by capacitor 19 of FIG. 2. First, the ground noise is discussed as an example: When the output capacitive load is being discharged by N-channel transistor 24, the voltage on the ground line will suddenly fluctuate in response to the discharge current passing through the ground line. This fluctuation of voltage, also called noise in this document, on the ground line is primarily a function of the inductance of the ground wires, the size of the output capacitive load being discharged, and the rate of current being discharged into the ground line. Thus, a reduction in the rate of current flow from the output pad capacitance 19 into the ground line (i.e. the discharge current) reduces the noise voltage on the ground line. Similarly, a reduction in the current flow into the output pad capacitance 19 from the supply voltage (i.e. the charge current) reduces the noise on the supply voltage line.
Moreover, the noise on the ground and the supply voltage lines, produced by the prior art predriver 18A and output driver 18B, further varies in response to the varying ambient temperature. For example, the peak noise level on the ground line at about 70.degree. C. ("hot" ambient condition) is approximately 0.9 volts as shown in FIG. 4. This peak noise level on the ground line is ordinarily tolerated in electronic systems. However, as also shown in FIG. 4, at about 0.degree. C. ("cold" ambient condition) this peak noise level exceeds 2.0 volts on the ground line. Thus, many electronic systems interpret this peak noise level at 0.degree. C. as a "One" rather than a "Zero." As such, this peak noise level causes many electronic systems to malfunction. A similar situation exists regarding the supply voltage noise. Thus, the foregoing discussion regarding the existence of excessive noise on ground line at 0.degree. C. also applies to the supply voltage line.
Therefore, it is critical to reduce the noise on the ground and the supply voltage lines such that the peak noise at 0.degree. C. is equal to the peak noise at 70.degree. C. and therefore a maximum peak noise of approximately 0.9 volts is achieved. The prior art has attempted to accomplish this objective primarily by slowing down the rate of current flow caused by the output driver circuit in discharging or charging the output pad capacitive load. Thus, the prior art slows down the output circuit for both the hot and cold ambient conditions. As such, the output circuit is unnecessarily slowed down at the hot ambient condition. It is noted that the slowing down of the output circuit at the hot ambient condition is, in addition to being unnecessary, further problematic since semiconductor devices already have their poorest speed performance at the hot ambient condition. Thus, although the prior art technique of slowing down the output driver circuit may achieve a reduced noise on the ground and the supply voltage lines, the prior art unnecessarily degrades the speed performance of the output circuit at the hot ambient conditions, where good speed performance is most needed.
It is therefore an object of the present invention to reduce the peak noise on the ground and the supply voltage lines produced by the macrocell of the present invention, while improving the overall speed of the macrocell. Thus, the present invention discloses a new design for Programmable Logic Device macrocells such that the peak noise on the ground and the supply voltage lines is significantly reduced, while the speed performance of the macrocell is also improved.